2,048k x 32 3.3v static ram module cym1861av33 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05297 rev. ** revised august 20, 2002 features ? high-density 3.3v 64-megabit sram module 32-bit standard footprint supports densities from 16k 32 through 2m 32 high-speed srams ? access time of 20 ns 72 pins available in simm format functional description the cym1861av33 is a high-performance 3.3v 64-megabit static ram module organized as 2,048k words by 32 bits. this module is constructed from sixteen 1,024k four srams in soj packages mounted on an epoxy laminate substrate. four chip selects are used to independently enable the four bytes. reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. the cym1861av33 is designed for use with standard 72-pin simm sockets. the pinout is downward compatible with the 64-pin jedec simm module family (cym1821, cym1831, cym1836, and cym1841). thus, a single motherboard design can be used to accommodate memory depth ranging from 16k words (cym1821) to 2,048k words (cym1861av33). the cym1861av33 is offered in vertical simm configuration and is available with tin-lead edge contacts. presence detect pins (pd 0 ? pd 3 ) are used to identify module memory density in applications where modules with alternate word depths can be interchanged. selection guide cy1861av33-20 cy1861av33-25 unit maximum access time 20 25 ns maximum operating current 2400 2400 ma maximum standby current 1050 1050 ma logic block diagram pin configuration a 0 ? a 19 oe i/o 0 ? i/o 3 cs 1 20 4 ? cs 4 pd 0 ? open pd 1 ? gnd pd 2 ? gnd pd 3 ? open we 1m x 4 sram zip/simm top view nc a 4 pd 3 pd 2 pd 0 gnd i/o 0 pd 1 i/o 1 i/o 8 i/o 2 i/o 9 i/o 3 v cc a 7 i/o 11 i/o 10 a 0 i/o 6 gnd nc a 15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 i/o 7 we a 8 a 9 i/o 4 i/o 5 a 14 cs 1 cs 3 a 16 gnd i/o 16 i/o 17 a 12 a 13 i/o 20 i/o 21 i/o 22 i/o 14 i/o 15 a 1 a 2 i/o 12 i/o 13 cs 2 i/o 18 i/o 19 a 10 a 11 cs 4 a 17 oe i/o 24 i/o 25 v cc a 6 i/o 28 i/o 29 i/o 26 i/o 27 a 3 a 5 66 68 70 65 67 69 i/o 23 gnd a 19 i/o 30 i/o 31 a 18 72 71 nc a 20 a 20 buffer mux i/o 4 ? i/o 7 4 i/o 8 ? i/o 11 4 1m x 4 sram i/o 12 i/o 15 4 i/o 16 i/o 19 4 1m x 4 sram i/o 20 i/o 23 4 i/o 24 i/o 27 4 1m x 4 sram i/o 28 i/o 31 4 ? ? ? ? ? i/o 0 ? i/o 3 4 1m x 4 sram i/o 4 ? i/o 7 4 i/o 8 ? i/o 11 4 1m x 4 sram i/o 12 i/o 15 4 i/o 16 i/o 19 4 1m x 4 sram i/o 20 i/o 23 4 i/o 24 i/o 27 4 1m x 4 sram i/o 28 i/o 31 4 ? ? ? ? ? 4:8
cym1861av33 document #: 38-05297 rev. ** page 2 of 7 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 55 c to +125 c ambient temperature with power applied............................................... ? 10 c to +85 c supply voltage to ground potential ............... ? 0.5v to +4.6v dc voltage applied to outputs in high-z state................................................ ? 0.5v to +v cc dc input voltage ............................................ ? 0.5v to +4.6v operating range range ambient temperature v cc commercial 0 c to +70 c 3.3 v + 10% ? 5% electrical characteristics over the operating range parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ? 0.3v 0.8 v i ix input load current gnd < v i < v cc ? 10 +10 a i oz output leakage current gnd < v o < v cc , output disabled ? 20 +20 a i cc v cc operating supply current v cc = max., i out = 0 ma, cs n < v il 2400 ma i sb1 automatic cs power-down current [1] max. v cc , cs > v ih , min. duty cycle = 100% 1050 ma i sb2 automatic cs power-down current [1] max. v cc , cs > v cc ? 0.2v, v in > v cc ? 0.2v, or v in < 0.2v 500 ma capacitance [2] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 7 pf c out output capacitance 14 pf ac test loads and waveforms notes: 1. a pull-up resistor to v cc on the cs input is required to keep the device deselected during v cc power-up, otherwise i sb will exceed values given. 2. tested on a sample basis. 90% 10% 3.3v gnd 90% 10% all input pulses 3.3v output 30 pf including jig and scope 3.3v output 5 pf including jig and scope (a) (b) <5ns <5 ns output r1 589 ? r1 589 ? r2 434 ? r2 434 ? 250 ? equivalent to: th venin equivalent 1.40v
cym1861av33 document #: 38-05297 rev. ** page 3 of 7 switching characteristics over the operating range [3] parameter description cy1861av33-20 cy1861av33-25 unit min. max. min. max. read cycle t rc read cycle time 20 25 ns t aa address to data valid 20 25 ns t oha data hold from address change 3 3 ns t acs cs low to data valid 20 25 ns t doe oe low to data valid 12 15 ns t lzoe oe low to low-z 0 4 ns t hzoe oe high to high-z 10 12 ns t lzcs cs low to low-z [4] 3 7 ns t hzcs cs high to high-z [4, 5] 10 12 ns t pd cs high to power-down 20 25 ns write cycle [6] t wc write cycle time 20 25 ns t scs cs low to write end 17 20 ns t aw address set-up to write end 17 20 ns t ha address hold from write end 3 3 ns t sa address set-up to write start 2 2 ns t pwe we pulse width 15 20 ns t sd data set-up to write end 12 15 ns t hd data hold from write end 2 2 ns t lzwe we high to low-z 3 3 ns t hzwe we low to high-z [5] 0 12 0 12 ns switching waveforms notes: 3. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 4. at any given temperature and voltage condition, t hzcs is less than t lzcs for any given device. these parameters are guaranteed and not 100% tested. 5. t hzcs and t hzwe are specified with c l = 5 pf as in (b) of ac test loads and waveforms. transition is measured 500 mv from steady-state voltage. 6. the internal write time of the memory is defined by the overlap of cs low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write. 7. we is high for read cycle. read cycle no. 1 previous data valid data valid t rc t aa t oha address data out [7, 8]
cym1861av33 document #: 38-05297 rev. ** page 4 of 7 notes: 8. device is continuously selected, cs = v il , and oe = v il . 9. address valid prior to or coincident with cs transition low. switching waveforms (continued) read cycle no. 2 data valid t rc t acs t doe t lzoe t lzcs high impedance t hzoe t hzcs high impedance data out oe cs v cc supply current 50% 50% t pu icc isb t pd [7, 9] write cycle no. 1 (we controlled) t wc data valid data undefined high impedance t scs t aw t sa t pwe t ha t hd t hzwe t lzwe t sd cs we address data in data out [6]
cym1861av33 document #: 38-05297 rev. ** page 5 of 7 switching waveforms (continued) write cycle no. 2 (cs controlled) t wc data valid data undefined high impedance t scs t aw t pwe t ha t hd t hzwe t sd cs we address data in data out t sa [6,10] truth table cs we oe inputs/output mode h x x high-z deselect/power-down l h l data out read llxdata in write l h h high-z deselect ordering information speed (ns) ordering code package type package type operating range 20 CYM1861AV33PM-20C pm48 72-pin plastic simm module commercial 25 cym1861av33pm-25c pm48 72-pin plastic simm module commercial note: 10. if cs goes high simultaneously with we high, the output remains in a high-impedance state.
cym1861av33 document #: 38-05297 rev. ** page 6 of 7 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. all product and company names mentioned in this document are the trademarks of their respective holders. package diagram 51-41322-*d 72-pin plastic simm module
cym1861av33 document #: 38-05297 rev. ** page 7 of 7 document title: cym1861av33 2,048k x 32 3.3v static ram module document number: 38-05297 rev. ecn no. issue date orig. of change description of change ** 117909 08/22/02 meg new data sheet
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